Integer Gate Logic Artificial Neural Network
Granted March 4, 2025. Covers foundational IGL architecture and learning mechanisms.
This foundational patent introduces Integer Gate Logic (IGL), an alternative artificial neural-network architecture that uses integer-valued weights, biases, and specialized non-monotonic activation functions to emulate Boolean logic gates and more complex nonlinear relationships. Individual computational nodes can reproduce functions such as AND, OR, XOR, XNOR, NAND, and NOR through different parameter configurations.
A central innovation is chain isolation optimization, a gradient-free training methodology that evaluates discrete parameter adjustments by recalculating the affected downstream computational chain rather than relying on conventional error backpropagation. Previously calculated outputs from unaffected nodes can be reused, potentially reducing redundant computation.
The patent also describes configurable network architectures, convolutional processing, enhanced error functions, training-data pruning, batch scheduling, and parallel processing techniques. These innovations establish the foundation for investigating compact, integer-based neural networks with efficient training and inference implementations across conventional processors, GPUs, and specialized hardware.
IGL Parallelization and Internal Visualization
Granted December 2, 2025. Covers additional IGL methods and capabilities.
This second patent extends the foundational Integer Gate Logic architecture with additional methods for efficient neural-network optimization, parallel processing, computational reuse, and internal network analysis.
The invention further develops chain isolation optimization by storing node inputs and outputs, evaluating discrete parameter changes, and selectively recalculating affected downstream computations to determine their impact on network error. The disclosed techniques support parallel evaluation strategies and lookup-table-based computation, providing opportunities to accelerate training on multicore processors, GPUs, and specialized computing hardware without conventional gradient backpropagation.
Additional innovations include ratcheting-threshold checkpoint training, which preserves improved parameter configurations and enables restoration when training performance deteriorates, as well as enhanced error-processing methods, adaptive training techniques, and internal network visualization.
Together, these developments expand IGL’s training and implementation capabilities, supporting research into scalable discrete optimization, computational efficiency, and more transparent analysis of neural-network behavior.